rev. 4.4 - 4/29/98 1 1 2 3 4 5 6 7 8 9 10 11 12 features n high-speed access times com?: 7, 8, 10, 12 and 15ns ind?: 8, 10, 12 and 15ns (use 15ns for slower designs) n low power operation (typical) - pdm41256sa active: 475 mw standby: 100 mw - pdm41256la active: 425mw standby: 25 mw n single +5v ( 10%) power supply n ttl-compatible inputs and outputs n packages plastic soj (300 mil) - so plastic tsop (i) - t description the pdm41256 is a high-performance cmos static ram organized as 32,768 x 8 bits. writing to this device is accomplished when the write enable (we ) and the chip enable (ce ) inputs are both low. reading is accomplished when we remains high and ce and oe are both low. the pdm41256 operates from a single +5v power supply and all the inputs and outputs are fully ttl- compatible. the pdm41256 comes in two versions: the standard power version pdm41256sa and the low power version pdm41256la. both versions are functionally the same and differ only in their power consumption. the pdm41256 is available in a 28-pin plastic tsop (i) and a 28-pin 300-mil plastic soj. a a 0 14 i/o i/o 0 7 ce we addresses decoder memory matrix input data control column i/o oe functional block diagram pdm41256 256k static ram 32k x 8-bit
pdm41256 2 rev. 4.4 - 4/29/98 oe
a11
a9
a8
a13
we
vcc
a14
a12
a7
a6
a5
a4
a3
21
20
19
18
17
16
15
14
13
12
11
10
9
8 a10
ce
i/o7
i/o6
i/o5
i/o4
i/o3
vss
i/o2
i/o1
i/o0
a0
a1
a2 22
23
24
25
26
27
28
1
2
3
4
5
6
7 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 a14
a12
a7
a6
a5
a4
a3
a2
a1
a0
i/o0
i/o1
i/o2
vss vcc
we
a13
a8
a9
a11
oe
a10
ce
i/o7
i/o6
i/o5
i/o4
i/o3 13 14 25 26 27 28 truth table note: 1. h = v ih , l = v il , x = don? care absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. 2. appropriate thermal calculations should be performed in all cases and speci?ally for those where the chosen package has a large thermal resistance (e.g., tsop). the calculation should be of the form : t j = t a + p * q ja where t a is the ambient tempera- ture, p is average operating power and q ja the thermal resistance of the package. for this product, use the following q ja values: soj: 78 o c/w tsop: 112 o c/w oe we ce i/o mode x x h hi-z standby lhld out read xlld in write h h l hi-z output disable symbol rating com l. ind. unit v term terminal voltage with respect to vss ?.5 to +7.0 ?.5 to +7.0 v t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma t j maximum junction temperature (2) 125 145 c pin con?urations tsop (i) soj pin description name description a14-a0 address inputs i/o7-i/o0 data inputs/outputs oe output enable input we write enable input ce chip enable input v cc power (+5v) v ss ground
pdm41256 rev. 4.4 - 4/29/98 3 1 2 3 4 5 6 7 8 9 10 11 12 recommended dc operating conditions dc electrical characteristics (v cc = 5.0v 10%) note: 1. v il (min) = ?.0v for pulse width less than 20 ns. power supply characteristics shaded area = preliminary data note:all values are maximum guaranteed values. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v v ss supply voltage 0 0 0 v commercial ambient temperature 0 25 70 c industrial ambient temperature ?0 25 85 c pdm41256sa pdm41256la unit symbol parameter test conditions min. max. min. max. i li input leakage current v cc = max., v in = vss to v cc com?/ ind. 55 11 m a i lo output leakage current v cc = max., ce = v ih , v out = vss to v cc com?/ ind. 55 11 m a v il input low voltage ?.5 (1) 0.8 ?.5 (1) 0.8 v v ih input high voltage 2.2 6.0 2.2 6.0 v v ol output low voltage i ol =8 ma, v cc = min. i ol = 10 ma, v cc = min. 0.4 0.5 0.4 0.5 v v oh output high voltage i oh = ? ma, v cc = min. 2.4 2.4 v -7 -8 -10 -12 -15 symbol parameter power com l. com l. ind. com l. ind. com l. ind. com l. ind. units i cc operating current ce = v il sa 210 200 210 190 200 170 180 150 160 ma f = f max = 1/t rc v cc = max i out = 0 ma la 190 180 190 170 180 150 160 130 140 ma i sb standby current ce = v ih sa 90 80 80 70 70 60 60 50 50 ma f = f max = 1/t rc v cc = max la 90 80 80 70 70 60 60 50 50 ma i sb1 full standby current ce 3 v cc ?0.2v sa 20 20 20 20 20 20 20 20 20 ma f = 0 v cc = max v in 3 v cc ?0.2v or 0.2v la 5555 55555ma
pdm41256 4 rev. 4.4 - 4/29/98 capacitance (1) (t a = +25 c, f = 1.0 mhz) note: 1. this parameter is determined by device characterization but is not production tested. ac test conditions symbol parameter max. unit c in input capacitance 8 pf c out output capacitance 8 pf input pulse levels v ss to 3.0v input rise and fall times 3 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 figure 1. output load equivalent figure 2. output load equivalent (for t lzce , t hzce , t lzwe , t hzwe , t lzoe , t hzoe ) +5v 480 w 255 w d out 30 pf +5v 480 w 255 w d out 5 pf 5 4 3 2 1 0 0 30 60 90 120 typical delta t aa vs capacitive loading additional lumped capacitive loading (pf) delta t aa - ns figure 3.
pdm41256 rev. 4.4 - 4/29/98 5 1 2 3 4 5 6 7 8 9 10 11 12 read cycle no. 1 (1) read cycle no. 2 (2) ac electrical characteristics shaded area = preliminary data. notes referenced are after data retention table. description --7 (6) --8 (6) -10 (6) -12 -15 read cycle sym min. max. min. max. min. max. min. max. min. max. units read cycle time t rc 7 8 101215 ns address access time t aa 7 8 10 12 15 ns chip enable access time t ace 7 8 10 12 15 ns output hold from address change t oh 3 3333ns chip enable to output in low z (3, 4, 5) t lzce 5 5555ns chip disable to output in high z (3, 4, 5) t hzce 56666ns chip enable to power up time (4) t pu 0 0000ns chip disable to power down time (4) t pd 7 8 10 12 15 ns output enable access time t aoe 55568ns output enable to output in low z (4, 5) t lzoe 0 0000ns output disable to output in high z (4, 5) t hzoe 56666ns t rc t aa t oh previous data valid d out addr data valid t rc t ace t aa t lzce t hzce t lzoe t hzoe t aoe addr ce oe d out data valid
pdm41256 6 rev. 4.4 - 4/29/98 write cycle no. 1 (write enable controlled) write cycle no. 2 (chip enable controlled) ac electrical characteristics description -7 (6) -8 (6) -10 (6) -12 -15 write cycle sym min. max. min. max. min. max. min. max. min. max. units write cycle time t wc 7 8 101215 ns chip enable to end of write t cw 7 8 101012 ns address valid to end of write t aw 7 8 101012 ns address setup time t as 0 0000ns address hold from end of write t ah 0 0000ns write pulse width t wp 7 8 8 8 11 ns data setup time t ds 6 7777ns data hold time t dh 0 0000ns write disable to output in low z (4, 5) t lzwe 0 0000ns write enable to output in high z (4, 5) t hzwe 33333ns t wc t aw t cw t ah t as t hzwe high z data valid t lzwe t ds t dh addr ce t wp we d in d out t wc t aw t cw t wp t ds data valid t dh t as addr d in undefined don't care t ah ce we shaded area = preliminary data
pdm41256 rev. 4.4 - 4/29/98 7 1 2 3 4 5 6 7 8 9 10 11 12 low v cc data retention waveform data retention electrical characteristics (la version only) notes: (for three previous electrical characteristics tables) 1. the device is continuously selected. chip enable is held in its active state. 2. the address is valid prior to or coincident with the latest occuring chip enable. 3. at any given temperature and voltage condition, t hzce is less than t lzce . 4. this parameter is sampled. 5. the parameter is tested with cl = 5 pf as shown in figure 2. transition is measured 200 mv from steady state voltage 6. vcc = 5v 5%. symbol parameter test conditions min. typ. max. unit v dr v cc for retention data 2 v i ccdr data retention current ce 3 v cc ?0.2v v in 3 v cc ?0.2v or 0.2v v cc = 2v 95 500 m a v cc = 3v 350 750 m a t cdr chip deselect to data retention time 0 ns t r (4) operation recovery time t rc ns don't care v cc v
v ih il t cdr v t r 4.5v 4.5v data retention mode ce dr v dr
pdm41256 8 rev. 4.4 - 4/29/98 ordering information device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) industrial (?0 c to +85 c) 7 8 10 12 15 (use 15ns for slower designs) sa standard power la low power blank i a automotive ( ?0 c to +105 c) blank tubes tr tape & reel ty tray pdm41256- 256k (32kx8) static ram xxxxx x xx x x x so 28-pin 300-mil plastic soj t 28-pin plastic tsop (i) commercial only faster memories for a faster world
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